Hello, I'm
Ph.D. Student in Electrical and Computer Engineering
University Distinguished Fellow @ Michigan State University
Conducting research at the intersection of machine learning and hardware architecture optimization to implement low-cost alternatives to deep physical tracking layouts.
Engineered embedded low-level acquisition logic and multi-core resource tracking mechanisms for next-generation XR device electronics hardware layers.
Developed validation tooling and internal scripts to streamline software deployment layers inside automotive electronic control units (ECUs).
Contributed to material characterization research pipelines aiming to systematically capture defect layout limits using digital ultrasonic parsing math.
Designed and verified a two-stage operational amplifier using SkyWater 130nm node technology inside Cadence Virtuoso. Modeled frequency compensation networks to ensure full stability, solid signal integrity, and robust noise immunity across the operating spectrum.
An 8-bit microprocessor datapath layout engineered inside a 0.5 µm CMOS process technology node. Fully integrates custom 6T SRAM storage layout configurations, an explicit Manchester carry-lookahead ALU, and logarithmic barrel shifters.
A high-performance, modular image augmentation toolkit built with a multithreaded architecture. Implements real-time structural transformation tasks through easy JSON configs.
A web application web framework project helping first-time pet owners understand pet emotions by parsing pose layout coordinates mapping to a classification network model architecture.
A portable solar hardware umbrella setup configured to dynamically gather solar arrays cleanly to support robust high-speed charging modules across smart portable electronics.